1. Field of the Invention
The present invention generally relates to generating a physical design for an integrated circuit chip. More particularly, the present invention relates to the field of method and system for creating a power distribution arrangement with tapered metal wires for a physical design.
2. Related Art
The process of generating a physical design for an integrated circuit chip is complicated. The physical design represents the layout of the integrated circuit chip on a semiconductor, such as silicon, and is utilized to fabricate the integrated circuit chip. There are several types of physical designs: flat physical designs and hierarchical physical designs. Typically, the physical design is generated in several stages. Examples of these stages include floorplanning, placement, routing, and verification. In a flat physical design, these stages are sequentially performed on the entire layout, while in a hierarchical physical design these stages are sequentially performed on partitions of the layout referred as blocks (or place-and-route blocks).
Floorplanning is performed before placement and routing. Thus, floorplanning affects subsequent stages such as placement and routing. The main goal and objective of floorplanning is creating a floorplan. The floorplan can determine whether placement and routing are possible for the physical design.
During the top-level floorplanning stage of a hierarchical physical design, blocks are arranged on a selected chip area and chip shape. In arranging the blocks, individual blocks are sized and shaped. These blocks can have any number of cells that execute digital or analog functions (e.g., NAND, NOR, D flip-flop, etc.) by convectively grouping circuit elements such as transistors, capacitors, resistors, and other circuit elements. Moreover, these blocks can have one or more macrocells. A macrocell is a functional module such as RAM, ROM, ALU, etc. Each of these cells and macrocells has one or more ports (or terminals) for inputting signals or outputting signals, each of which, in turn, may connect to one or more ports of other cells and macrocells via metal wires. A net is a set of two or more ports that are connected. Generally, the input to the floorplanning stage is a netlist for the integrated circuit chip. A netlist is a list of nets for the integrated circuit chip.
Continuing, the location of Input/Output blocks is determined. These Input/Output blocks facilitate connections/communication with external components. An Input/Output block may have bonding pad cells or bump cells. Moreover, power distribution and clock distribution are determined during the top-level floorplanning stage of the hierarchical physical design. Furthermore, the top-level floorplanning stage is performed with the objectives of minimizing the chip area and minimizing delay.
FIG. 1A illustrates a power distribution arrangement 100 for a physical design (flat or hierarchical) of the prior art. As shown in FIG. 1A, the power distribution arrangement 100 has a plurality of metal wires 10 and 20 arranged in a mesh shape. Moreover, the vertical metal wires 10 are formed using a first metal layer while the horizontal metal wires 20 are formed using a second metal layer. The first and second metal layers are typically higher-level metal layers instead of lower-level metal layers. As depicted in FIG. 1A, the first metal layer is metal layer 7 while the second metal layer is metal layer 6. In general, metal wires comprised of one or more other metal layers appropriately couple the vertical and horizontal metal wires 10 and 20 to cells and macrocells. Power or ground is commonly provided in an alternating manner to the vertical metal wires 10 and the horizontal metal wires 20. Furthermore, the width 50 of the metal wire 45 used for the vertical metal wires 10 and the horizontal metal wires 20 is typically uniform or constant, as shown in FIG. 1B.